preliminary 256k x 24 static ram module cym26kah24av33 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-05324 rev. ** revised january 17, 2003 features ? high-density 6-megabit sram module high-speed cmos srams ?t aa = 10 ns single 3.3v power supply low active power(648 w at 10 ns) ttl-compatible inputs and outputs available in standard 119-ball bga functional description the cym26kah24av33 is a 3.3v high-performance 6-megabit static ram organized as a 256k words by 24 bits. this module is constructed from two sram dies mounted on a multilayer laminate substrate combined to form a 24-bit sram. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data from i/o pins (i/o 0 through i/o 23 ), is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. then data from the memory location specified by the address pins will appear on i/o 0 to i/o 23 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 23 ) are placed in a high-impedance state when the device is deselected (ce high), and the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cym26kah24av33 is available in a standard 119 bga. selection guide -10 -12 unit maximum access time 10 12 ns maximum operating current commercial 180 170 ma industrial 200 190 ma maximum standby current commercial industrial 20 20 ma functional block diagram a[17:0] we/ oe/ ce/ i/o 0-23 i/o 0-11 i/o 12-23 i/o 0-11 i/o 12-23 ce0/ a[17:0] a[17:0] ce1/ we0/ oe0/ oe1/ we1/
preliminary cym26kah24av33 document #: 38-05324 rev. ** page 2 of 8 note: 1. bumps 3c and 5c are actually nc ? s but they should be wired 3c to v cc and 5c to vss to assure compatibility with future versions. pin configurations 119 bga top view 1234567 a nc a a a a a nc b nc a a ce aanc c i/o 12 nc nc [1] anc [1] nc i/0 11 d i/o 13 v cc v ss v ss v ss v cc i/o 10 e i/o 14 nc v cc v ss v cc nc i/o 9 f i/o 15 v cc v ss v ss v ss v cc i/o 8 g i/o 16 nc v cc v ss v cc nc i/o 7 h i/o 17 v cc v ss v ss v ss v cc i/o 6 j v cc v ss v cc v ss v cc v ss v dd k i/o 18 v cc v ss v ss v ss v cc i/o 5 l i/o 19 nc v cc v ss v cc nc i/o 4 m i/o 20 v cc v ss v ss v ss v cc i/o 3 n i/o 21 nc v cc v ss v cc nc i/o 2 p i/o 22 v cc v ss v ss v ss v cc i/o 1 r i/o 23 nc nc nc nc nc i/o 0 t nc a a we aanc u nc a a oe aanc
preliminary cym26kah24av33 document #: 38-05324 rev. ** page 3 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................ ? 65 c to +150 c ambient temperature with power applied .. ? 55 c to +125 c supply voltage on v cc to relative gnd [2] ...... ? 0.5v to 4.6v dc voltage applied to outputs in high-z state [2] .................................... ? 0.5v to v cc + 0.5v dc input voltage [2] ................................. ? 0.5v to v cc + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage........................................... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 5% industrial ? 40 c to +85 c 3.3v 5% electrical characteristics over the operating range parameter description test conditions -10 -12 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [2] ? 0.3 0.8 -0.3 0.8 v i ix input load current gnd < v i < v cc ? 2+2 -2 +2 a i oz output leakage current gnd < v i < v cc , output disabled ? 2+2 -2 +2 a i cc v cc operating supply current v cc = max. f = f max = 1/t rc commercial 180 170 ma industrial 200 190 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 80 80 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 commercial/ industrial 20 20 ma capacitance [2] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 8 pf ac test loads and waveforms note: 2. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 5 pf including jig and scope (a) (b) 3 ns 3ns r1 317 ? r2 351 ? utput r l = 50 ? z 0 = 50 ? v th = 1.5v
preliminary cym26kah24av33 document #: 38-05324 rev. ** page 4 of 8 ac switching characteristics [3] over the operating range parameter description -10 -12 unit min. max. min. max. read cycle t rc read cycle time 10 12 ns t aa address to data valid 10 12 ns t oha data hold from address change 3 3 ns t ace ce active to data valid 10 12 ns t doe oe low to data valid 5 6 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [4, 5] 56ns t lzce ce active to low z [5] 33ns t hzce ce inactive to high z [4, 5] 56ns t pu ce active to power-up 0 0 ns t pd ce inactive to power-down 10 12 ns write cycle [6, 7] t wc write cycle time 10 12 ns t sce ce active to write end 7 8 ns t aw address set-up to write end 7 8 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 7 8 ns t sd data set-up to write end 5 6 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [5] 33ns t hzwe we low to high z [4, 5] 45ns switching waveforms read cycle no. 1 [8, 9] notes: 3. tested initially and after any design or process changes that may affect these parameters. 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh . 5. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal t hat terminates the write. 8. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 9. device is continuously selected. oe , ce = v il . previous data valid data valid t rc t aa t oha address data out
preliminary cym26kah24av33 document #: 38-05324 rev. ** page 5 of 8 read cycle no. 2 (oe controlled) [10, 11] write cycle no. 1 (ce controlled) [12, 13] notes: 10. we is high for read cycle. 11. address valid prior to or coincident with ce transition low. 12. data i/o is high impedance if oe = v ih . 13. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o
preliminary cym26kah24av33 document #: 38-05324 rev. ** page 6 of 8 ordering information write cycle no. 2 (we controlled, oe high during write) write cycle no. 3 (we controlled, oe low) switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 14 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 14 speed (ns) ordering code package name package type operating range 10 CYM26KAH24AV33-10BGC bg119 119-ball bga commercial 10 cym26kah24av33-10bgi bg119 119-ball bga industrial 12 cym26kah24av33-12bgc bg119 119-ball bga commercial 12 cym26kah24av33-12bgi bg119 119-ball bga industrial note: 14. during this period the i/os are in the output state and input signals should not be applied.
preliminary cym26kah24av33 document #: 38-05324 rev. ** page 7 of 8 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. all product and company names mentioned in this document are the trademarks of their respective holders. package diagram 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
preliminary cym26kah24av33 document #: 38-05324 rev. ** page 8 of 8 document history page document title: cym26kah24av33 256k x 24 static ram module document number: 38-05324 rev. ecn no. issue date orig. of change description of change ** 123014 01/22/03 cs new data sheet
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